Multi-domain liquid crystal display and a thin film transistor substrate of the same

ABSTRACT

A thin film transistor array panel is provided, which includes: a gate wire formed on an insulating substrate; a data wire formed on the insulating substrate, insulated from the gate wire, and intersecting the gate wire; a storage electrode wire formed on the insulating substrate, insulated from the data wire, and intersecting the data wire; a plurality of pixel electrodes provided on the respective pixel areas defined by the intersections of the gate wire and the data wire, each pixel electrode having a cutout; a plurality of direction control electrodes provided on the respective pixel areas defined by the intersections of the gate wire and the data wire; a plurality of first thin film transistors connected to the gate wire, the data wire, and the pixel electrodes; and a plurality of second thin film transistors connected to the gate wire, the storage electrode wire, and the direction control electrodes.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a liquid crystal display, and inparticular, vertically-aligned liquid crystal display having a pixelregion including a plurality of domains for wide viewing angle.

(b) Description of the Related Art

A typical liquid crystal display (LCD) includes an upper panel providedwith a common electrode and an array of color filters, a lower panelprovided with a plurality of thin film transistors (TFTs) and aplurality of pixel electrodes, and a liquid crystal layer is interposedtherebetween. The pixel electrodes and the common electrode are appliedwith electric voltages and the voltage difference therebetween causeselectric field. The variation of the electric field changes theorientations of liquid crystal molecules in the liquid crystal layer andthus the transmittance of light passing through the liquid crystallayer. As a result, the LCD displays desired images by adjusting thevoltage difference between the pixel electrodes and the commonelectrode.

The LCD has a major disadvantage of its narrow viewing angle, andseveral techniques for increasing the viewing angle have been developed.Among these techniques, the provision of a plurality of cutouts or aplurality of projections on the pixel electrodes and the commonelectrode opposite each other along with the vertical alignment of theliquid crystal molecules with respect to the upper and the lower panelsis promising.

The cutouts provided both at the pixel electrodes and the commonelectrode give wide viewing angle by generating fringe field to adjustthe tilt directions of the liquid crystal molecules.

The provision of the projections both on the pixel electrode and thecommon electrode distorts the electric field to adjust the tiltdirections of the liquid crystal molecules.

The fringe field for adjusting the tilt directions of the liquid crystalmolecules to form a plurality of domains is also obtained by providingthe cutouts at the pixel electrodes on the lower panel and theprojections on the common electrode on the upper panel.

Among these techniques for widening the viewing angle, the provision ofthe cutouts has problems that an additional mask for patterning thecommon electrode is required, an overcoat is required for preventing theeffect of the pigments of the color filters on the liquid crystalmaterial, and severe disclination is generated near the edges of thepatterned electrode. The provision of the projections also has a problemthat the manufacturing method is complicated since it is required anadditional process step for forming the projections or a modification ofa process step. Moreover, the aperture ratio is reduced due to theprojections and the cutouts.

SUMMARY OF THE INVENTION

It is a motivation of the present invention to provide a liquid crystaldisplay manufactured by simple process and ensuring stablemulti-domains.

These and other motivation may be achieved by providing a pixel thinfilm transistor for a pixel electrode and a direction-control-electrodethin film transistor for a direction control electrode. The pixel thinfilm transistor transmits signals from a data line and thedirection-control-electrode thin film transistor transmits signals froma storage electrode wire.

A thin film transistor array panel is provided, which includes: aninsulating substrate; a plurality of first signal lines formed on theinsulating substrate; a plurality of second signal lines formed on theinsulating substrate, insulated from the first signal lines, andintersecting the first signal lines; a plurality of third signal linesformed on the insulating substrate, insulated from the second signallines, and intersecting the second signal lines; a plurality of pixelelectrodes provided on respective pixel areas defined by theintersections of the first and the second signal lines, each pixelelectrode having a cutout; a plurality of direction control electrodesprovided on the respective pixel areas defined by the intersections ofthe first and the second signal lines; a plurality of first thin filmtransistors, each first thin film transistor connected to one of thefirst signal lines, one of the second signal lines, and one of the pixelelectrodes; and a plurality of second thin film transistors, each secondthin film transistor connected to one of the first signal lines, one ofthe third signal lines, and one of the direction control electrodes.

Preferably, one of the first thin film transistors and one of the secondthin film transistor located on one of the pixel areas are connected toa relevant one of the first signal lines and a previous one of the firstsignal lines.

A thin film transistor array panel is provided, which includes: aninsulating substrate; a gate wire formed on the insulating substrate andincluding first and second gate electrodes and a plurality of gatelines; a storage electrode wire formed on the insulating substrate andincluding a plurality of storage electrode lines and a plurality ofstorage electrodes; a gate insulating layer formed on the gate wire andthe storage electrode wire; a semiconductor layer formed on the gateinsulating layer; a data wire formed on the semiconductor layer andincluding a plurality of data lines intersecting the gate lines, aplurality of first source electrodes connected to the data lines, aplurality of first drain electrodes opposite the first source electrodeswith respect to the first gate electrodes, a plurality of second sourceelectrodes electrically connected to the storage electrode wire, and aplurality of second drain electrodes opposite the second sourceelectrodes with respect to the second gate electrodes; a directioncontrol electrode connected to the second drain electrode; a passivationlayer formed on the data wire and the direction control electrode andhaving a plurality of contact holes; and a pixel electrode formed on thepassivation layer, having a plurality of cutouts, and electricallyconnected to the first drain electrodes through the contact holes.

The direction control electrode overlaps the cutouts of the pixelelectrode at least in part. The cutouts of the pixel electrode may havea plurality of X-shaped cutouts and a plurality of rectilinear cutoutsand the direction control electrode preferably overlaps the X-shapedcutouts. The semiconductor layer preferably includes a plurality of dataportions disposed under the data lines, a plurality of first channelportions disposed under the first source electrodes and the first drainelectrodes, and a plurality of second channel portions disposed underthe second source electrodes and the second drain electrodes. The thinfilm transistor array panel may further include a plurality ofconnecting members formed on the passivation layer and connecting thesecond source electrodes and the storage electrode wire through contactholes provided at the passivation layer and the gate insulating layer.The direction control electrode preferably includes substantially thesame layer and material as the data wire.

A liquid crystal display is provided, which includes: a first insulatingsubstrate; a plurality of first signal lines formed on the firstinsulating substrate; a plurality of second signal lines formed on thefirst insulating substrate, insulated from the first signal lines, andintersecting the first signal lines; a plurality of third signal linesformed on the first insulating substrate, insulated from the secondsignal lines, and intersecting the second signal lines; a plurality ofpixel electrodes provided on the respective pixel areas defined by theintersections of the first and the second signal lines, each pixelelectrode having a cutout; a plurality of direction control electrodesprovided on the respective pixel areas defined by the intersections ofthe first and the second signal lines; a plurality of switchingelements, each first switching element connected to one of the firstsignal lines, one of the second signal lines, and one of the pixelelectrodes; a plurality of second thin film transistors, each secondswitching element connected to one of the first signal lines, one of thethird signal lines, and one of the direction control electrodes; asecond insulating substrate opposite the first insulting substrate; acommon electrode formed on the second insulating substrate; and a liquidcrystal layer interposed between the first insulating substrate and thesecond insulating substrate.

The third signal lines are preferably supplied with a voltage to beapplied to the common electrode. The liquid crystal layer has negativedielectric anisotropy and major axes of liquid crystal molecules in theliquid crystal layer are aligned vertical to the first and the secondsubstrates. Otherwise, the liquid crystal layer has positive dielectricanisotropy and major axes of liquid crystal molecules in the liquidcrystal layer are aligned parallel to the first and the secondsubstrates.

A thin film transistor array panel is provided, which includes: aninsulating substrate; a gate wire formed on the insulating substrate; astorage electrode wire formed on the insulating substrate; a gateinsulating layer formed on the gate wire and the storage electrode wire;a data wire formed on the gate insulating layer including three layersan amorphous silicon layer, a doped amorphous silicon layer, and a metallayer; a direction control electrode formed on the gate insulatinglayer, including three layers an amorphous silicon layer, a dopedamorphous silicon layer, and a metal layer, and electrically connectedto the second drain electrode; a passivation layer formed on the datawire and the direction control electrode and having a plurality ofcontact holes; and a pixel electrode formed on the passivation layer,having a plurality of cutouts, and electrically connected to the datawire through the contact holes.

It is preferable that the gate wire comprises first and second gateelectrodes, the data wire comprises first and second source electrodesand first and second drain electrodes, the direction control electrodeis connected to the second drain electrode, the pixel electrode isconnected to the first drain electrode, and the second source electrodeis connected to the storage electrode wire. The thin film transistorarray panel may include a connecting member formed on the passivationlayer and connecting the second source electrode and the storageelectrode wire through a contact hole provided at the passivation layerand the gate insulating layer.

A method of manufacturing a thin film transistor array panel isprovided, which includes: forming a gate wire and a storage electrodewire; depositing a gate insulating layer, an amorphous silicon layer, acontact layer, and a metal conductive layer; patterning the amorphoussilicon layer, the contact layer, and the metal conductive layer to forma data wire, a direction control electrode, and a channel portion of athin film transistor; forming a passivation layer on the channelportion; and forming a pixel electrode and a connecting portion on thepassivation layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an equivalent circuit diagram of an LCD according to anembodiment of the present invention;

FIG. 2A is a layout view of a TFT array panel for an LCD according to afirst embodiment of the present invention;

FIGS. 2B and 2C are sectional views of the TFT array panel shown in FIG.2A taken along the lines IIb-IIb′ and IIc-IIc′, respectively;

FIGS. 3A to 3D are sectional views of a TFT array panel for an LCDsequentially illustrating a manufacturing method thereof according to afirst embodiment of the present invention;

FIG. 4 is a layout view of a TFT array panel for an LCD according to asecond embodiment of the present invention;

FIG. 5 is a sectional view of the TFT array panel shown in FIG. 4 takenalong the lines V-V′ and V′-V″;

FIGS. 6A to 11B are layout views and sectional views of a TFT arraypanel for an LCD sequentially illustrating a manufacturing methodthereof according to a second embodiment of the present invention;

FIG. 12 is a schematic diagram of TFT array panels for an LCD accordingto first and second embodiments of the present invention; and

FIG. 13 is a picture image on an LCD according to an embodiment of thepresent invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the inventions invention are shown. The present invention may,however, be embodied in many different forms and should not be construedas limited to the embodiments set forth herein.

In the drawings, the thickness of layers and regions are exaggerated forclarity. Like numerals refer to like elements throughout. It will beunderstood that when an element such as a layer, region or substrate isreferred to as being “on” another element, it can be directly on theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly on” another element,there are no intervening elements present.

Now, LCDs according to embodiments of this invention will be describedin detail with reference to the accompanying drawings.

FIG. 1 is an equivalent circuit diagram of an LCD according to anembodiment of the present invention.

An LCD according to an embodiment of the present invention includes aTFT array panel, a color filter array panel opposite the TFT arraypanel, and a liquid crystal layer interposed therebetween. The TFT arraypanel is provided with a plurality of gate lines and a plurality of datalines intersecting each other to define a plurality of pixel areas, anda plurality of storage electrode lines extending parallel to the gatelines. The gate lines transmit scanning signals and the data linestransmit image signals. A common voltage Vcom is applied to the storageelectrode lines. Each pixel area is provided with a pixel TFT for apixel electrode and a direction-control-electrode TFT DCETFT for adirection control electrode (“DCE”). Tie pixel TFT includes a gateelectrode connected to one of the gate lines, a source electrodeconnected to one of the data lines, and a drain electrode connected toone of a plurality of pixel electrodes, while the DCE TFT includes agate electrode connected to a previous gate line, a source electrodeconnected to one of the storage electrode lines, and a drain electrodeconnected to one of a plurality of direction control electrodes.

The DCE and the pixel electrode are capacitively coupled, and thecapacitor therebetween or its capacitance is represented by C_(DP). Thepixel electrode and a common electrode provided on the color filterarray panel form a liquid crystal capacitor, and the liquid crystalcapacitor or its capacitance is represented by C_(LC). The pixelelectrode and a storage electrode connected to one of the storageelectrode lines form a storage capacitor, and the storage capacitor orits capacitance is represented by C_(ST).

Although it is not shown in the circuit diagram, the pixel electrodeaccording to an embodiment of the present invention has an apertureoverlapping the DCE such that the electric field due to the DCE flowsout through the aperture. The electric field flowing out through theaperture makes the liquid crystal molecules have pretilt angles. Thepretilted liquid crystal molecules are rapidly aligned withoutdispersion along predetermined directions upon the application of theelectric field due to the pixel electrode.

In order to obtain the pretilted liquid crystal molecules using theelectric field generated by the DCE, the potential of the DCE relativeto the potential of the common electrode (referred to as the “DCEvoltage” hereinafter) is larger than the potential of the pixelelectrode relative to the potential of the common electrode (referred toas the “pixel voltage” hereinafter) by a predetermined value. The LCDaccording to an embodiment of the present invention easily satisfiesthis requirement by isolating the DCE after applying the potentialapplied to the storage electrode lines to the DCE. The reason will bedescribed now.

Consider a moment that a given pixel electrode having a negativepotential is refreshed by a positive potential. The application of agate-on signal to the previous gate line turns on the DCE TFT to makethe DCE have a potential higher than the pixel electrode. This changesthe potential of the pixel electrode capacitively coupled with the DCE.In this case, the capacitor C_(DP) between the DCE and the pixelelectrode and the capacitor C_(LC) between the pixel electrode and thecommon electrode are connected in series. Since the pixel electrode hadthe negative potential, its potential is lower than that of the DCE,i.e., V_(DCE)>V_(P) during the charging of the serially-connectedcapacitors C_(DP) and C_(LC). When the DCE TFT is turned off aftercharging, the DCE floats. Accordingly, the potential of the DCE isalways larger than the potential of the pixel electrode irrespective ofthe potential change of the pixel electrode. For example, when thepotential of the pixel electrode is increased to a positive value whenthe pixel TFT is turned on, the potential of the DCE follows thepotential increase of the pixel electrode in order to maintain thepotential difference between the DCE and the pixel electrode.

This is described in terms of an electrical circuit.

A voltage across a capacitor in an electrical circuit is given by:

$\begin{matrix}{V_{C} = {V_{0} + {\frac{1}{C}{\int_{0}^{t}{i\ {\mathbb{d}(t)}}}}}} & (1)\end{matrix}$

A floating electrode is equivalent to an electrode connected to aresistor having infinite resistance (R=∞). Therefore, i=0 andV_c=V_(—)0, that is, the initial voltage across the capacitor ismaintained. In other words, the potential of a floating electrodeincreases or decreases coupled with the potential of the otherelectrode.

On the contrary, when refreshing with a negative potential, thepotential of the DCE is always lower than the potential of the pixelelectrode by a predetermined value.

According to an embodiment of the present invention, the DCE TFT isconnected to the storage electrode lines such that the common voltage isapplied to the DCE. Hence, the potentials of the two electrodesincreases or decreases to have substantially the same polarityirrespective of the polarity of the potential applied to the pixelelectrode in the next frame. As a result, the present invention isapplied any inversion type such as line inversion and dot inversion.

For the same gray, there is no variation of the potential differencebetween the DCE and the pixel electrode irrespective of the grays ofprevious and next frames, thereby ensuring stability of image quality.

The disconnection of the DCE TFTs from the data lines prevents theincrease of the load of the data lines.

Now, a detailed embodiment of the present invention is described withreference to FIGS. 2A to 2C.

FIG. 2A is a layout view of an LCD according to an embodiment of thepresent invention, and FIGS. 2B and 2C are sectional views of the LCDshown in FIG. 2A taken along the lines IIB-IIB′.

An LCD according to a first embodiment of the present invention includesa lower panel, an upper panel facing the lower panel, and a vertically(or homeotropically) aligned liquid crystal layer interposed between thelower panel and the upper panel.

The lower panel will now be described more in detail.

A plurality of gate lines 121 are formed on an insulating substrate 110and a plurality of data lines 171 are formed thereon. The gate lines 121and the data lines 171 are insulated from each other and intersect eachother to define a plurality of pixel areas.

Each pixel area is provided with a pixel TFT, a DCE TFT, a DCE and apixel electrode. The pixel TFT has three terminals, a first gateelectrode 123 a, a first source electrode 173 a and a first drainelectrode 175 a while the DCE TFT has three terminals, a second gateelectrode 123 b, a second source electrode 173 b and a second drainelectrode 175 b. The pixel TFT is provided for switching the signalstransmitted to the pixel electrode 190 while the DCE TFT is provided forswitching the signals entering the DCE 176. The gate electrode 123 a,the source electrode 173 a and the drain electrode 175 of the pixel TFTare connected to corresponding one of the gate lines 121, one of thedata lines 171 and the pixel electrode 190, respectively. The gateelectrode 123 b, the source electrode 173 b and the drain electrode 175b of the DCE TFT are connected to previous one of the gate lines 121,corresponding one of the storage electrode lines 131 and the DCE 176,respectively. The DCE 176 is applied with a direction-controllingvoltage for controlling the pre-tilts of the liquid crystal molecules togenerate a direction-controlling electric field between the DCE 176 andthe common electrode 270. The DCE 176 is formed in a step for formingthe data lines 171.

The layered structure of the lower panel will be described in detail.

A plurality of gate lines 121 extending substantially in a transversedirection are formed on an insulating substrate 110, and a plurality offirst and second gate electrodes 123 a and 123 b are connected to thegate lines 121. A plurality of storage electrode lines 131 and aplurality of sets of first to fourth storage electrodes 133 a-133 d arealso formed on the insulating substrate 110. The storage electrode lines131 extend substantially in the transverse direction, and the first andthe second storage electrodes 133 a and 133 b extend from the storageelectrode line 131 in a longitudinal direction. The third and the fourthstorage electrodes 133 c and 133 d extend in the transverse directionand connect the first storage electrode 133 a and the second storageelectrode 133 b.

The gate wire 121, 123 a and 123 b and the storage electrode wire 131and 133 a-133 d are preferably made of Al, Cr or their alloys, Mo or Moalloy. If necessary, the gate wire 121, 123 a and 123 b and the storageelectrode wire 131 and 133 a-133 d include a first layer preferably madeof Cr or Mo alloys having excellent physical and chemicalcharacteristics and a second layer preferably made of Al or Ag alloyshaving low resistivity.

A gate insulating layer 140 is formed on the gate wire 121, 123 a and123 b and the storage electrode wire 131 and 133 a-133 d.

A semiconductor layer 151 a, 151 b, 153 and 155 preferably made ofamorphous silicon is formed on the gate insulating layer 140. Thesemiconductor layer 151 a, 151 b, 153 and 155 includes a plurality offirst and second channel semiconductors 151 a and 151 b forming channelsof TFTs, a plurality of data-line semiconductors 153 located under thedata lines 171, and a plurality of intersection semiconductors 155located near the intersections of DCEs 176 and the storage electrodes133 c and 133 d for ensuring insulation therebetween.

An ohmic contact layer 161, 163 a, 163 b, 165 a and 165 b preferablymade of silicide or n+ hydrogenated amorphous silicon heavily doped withn type impurity is formed on the semiconductor layer 151 a, 151 b, 153and 155.

A data wire 171, 173 a, 173 b, 175 a and 175 b is formed on the ohmiccontact layer 161, 163 a, 163 b, 165 a and 165 b and the gate insulatinglayer 140. The data wire 171, 173 a, 173 b, 175 a and 175 b includes aplurality of data lines 171 extending in the longitudinal direction andintersecting the gate lines 121 to form a plurality of pixels, aplurality of first source electrodes 173 a branched from the data lines171 and extending onto portions 163 a of the ohmic contact layer, aplurality of first drain electrodes 175 a disposed on portions 165 a ofthe ohmic contact layer, located opposite the first source electrodes173 a with respect to the first gate electrodes 123 a and separated fromthe first source electrodes 173 a, a plurality of second sourceelectrodes 173 b and a plurality of second drain electrodes 175 bdisposed on respective portions 163 b and 165 b opposite each other withrespect to the second gate electrodes 123 b, and a plurality of datapads (not shown) connected to one ends of the data lines 171 to receiveimage signals from an external device.

A plurality of DCEs 176 are formed in the pixel areas defined by theintersections of the gate lines 121 and the data lines 171. Each DCE 176includes a plurality of X-shaped metal pieces connected to one anotherand is connected to the second drain electrode 175 b. The data wire 171,173 a, 173 b, 175 a and 175 b and the DCEs 176 are preferably made ofAl, Cr or their alloys, Mo or Mo alloy. If necessary, the data wire 171,173 a, 173 b, 175 a and 175 b and the DCEs 176 include a first layerpreferably made of Cr or Mo alloys having excellent physical andchemical characteristics and a second layer preferably made of Al or Agalloys having low resistivity.

A passivation layer 180 preferably made of silicon nitride or organicinsulator is formed on the data wire 171, 173 a, 173 b, 175 a and 175 b.

The passivation layer 180 is provided with a plurality of contact holes181 exposing the first drain electrodes 175 a, a plurality of contactholes 182 extending to the gate insulating layer 140 and exposing thestorage electrode lines 131, a plurality of contact holes 183 exposingthe second source electrodes 173 b, a plurality of contact holes (notshown) exposing the data pads, and a plurality of contact holes (notshown) extending to the gate insulating layer 140 exposing the gatepads. The contact holes exposing the pads may have various shapes suchas polygon or circle. The area of the contact hole is preferably equalto or larger than 0.5 mm×15 μm and not larger than 2 mm×60 μm.

A plurality of pixel electrodes 190 are formed on the passivation layer180. Each pixel electrode 190 is connected to the first drain electrode175 a through the contact hole 181 and has a plurality of X-shapedcutouts 191 and a plurality of linear cutouts 192. The X-shaped cutouts191 overlap the X-shaped portions of the DCE 176 while the linearcutouts 192 overlap the third and the fourth storage electrodes 133 cand 133 d. The DCE 176 broadly overlaps peripheries of the cutouts 191as well as the cutouts 191 themselves to form a storage capacitancealong with the pixel electrode 190.

A plurality of bridges 92 connecting the storage electrode lines 131 andthe second source electrodes 173 b through the contact holes 182 and 183are also formed on the passivation layer. Furthermore, a plurality ofsubsidiary gate pads (not shown) and a plurality of subsidiary data pads(not shown) are formed on the passivation layer 180. The subsidiary gatepads and the subsidiary data pads are connected to the gate pads and thedata pads through the contact holes. The pixel electrodes 190, thebridges 92, the subsidiary gate pads and the subsidiary data pads arepreferably formed of indium zinc oxide (“IZO”). Alternatively, the pixelelectrodes 190, the bridges 92 and the subsidiary pads are preferablymade of indium tin oxide (“ITO”).

To summarize, each pixel electrode 190 has the plurality of cutouts 191and 192 for partitioning a pixel region into a plurality of domains, andthe first cutouts 191 overlap the DCE 176 while the second cutouts 192overlap the storage electrodes 133 c and 133 d. The DCE 176 and thefirst cutouts 191 are aligned such that the DCE 176 is exposed throughthe first cutouts 191 to be seen in front view. The storage electrodeline 131 and the DCE 176 are connected via the DCE TFT while the dataline 171 and the pixel electrode 190 are connected via the pixel TFT,and the pixel electrode 190 and the DCE 176 are aligned to form astorage capacitance.

According to another embodiment of the present invention, the DCEs 176include substantially the same layer as the gate wire 121, 123 a and 123b. The portions of the passivation layer 180 on the DCEs 176 may beremoved to form a plurality of openings.

The upper substrate 210 will now be described in detail.

A black matrix 220 for preventing light leakage, a plurality of red,green and blue color filters 230, and a common electrode 270 preferablymade of a transparent conductor such as ITO or IZO are formed on anupper substrate 210 preferably made of transparent insulating materialsuch glass.

A plurality of liquid crystal molecules contained in the liquid crystallayer 3 is aligned such that their director is perpendicular to thelower and the upper substrates 110 and 210 in absence of electric field.The liquid crystal layer 3 has negative dielectric anisotropy.

The lower substrate 110 and the upper substrate 210 are aligned suchthat the pixel electrodes 190 exactly match and overlap the colorfilters 230. In this way, a pixel region is divided into a plurality ofdomains by the cutouts 191 and 192. The alignment of the liquid crystallayer 3 in each domain is stabilized by the DCE 176.

This embodiment illustrates the liquid crystal layer 3 having negativedielectric anisotropy and homeotropic alignment with respect to thesubstrates 110 and 210. However, the liquid crystal layer 3 may havepositive dielectric anisotropy and homogeneous alignment with respect tothe substrates 110 and 210.

A method of manufacturing a TFT array panel of an LCD having theabove-described structure will be described.

FIGS. 3A to 3D are sectional views of a TFT array panel for an LCDsequentially illustrating a manufacturing method thereof according to afirst embodiment of the present invention.

First, as shown in FIG. 3A, a conductive layer preferably made of metalis deposited by sputtering and either dry-etched or wet-etched by afirst photo-etching step using a mask to form a gate wire and a storageelectrode wire on a substrate 110. The gate wire includes a plurality ofgate lines 121, a plurality of gate pads (not shown) and a plurality ofgate electrodes 123, and the storage wire includes a plurality ofstorage electrode lines 131 and a plurality of storage electrodes 133a-133 d.

As shown in FIG. 3B, a gate insulating layer 140 with 1,500-5,000 Åthickness, a hydrogenated amorphous silicon layer with 500-2,000 Åthickness, and a doped amorphous silicon layer with 300-600 Å thicknessare sequentially deposited by chemical vapor deposition (“CVD”). Thedoped amorphous silicon layer and the amorphous silicon layer arepatterned by a photo-etching step using a mask to form an ohmic contactlayer 160 a, 160 b and 161 and an amorphous silicon layer 151 a, 151 band 153.

Thereafter, as shown in FIG. 3C, a conductive layer with 1,500-3,000 Åthickness preferably made of metal is deposited by sputtering andpatterned by a photo-etching step using a mask to form a data wire and aplurality of DCEs 176. The data wire includes a plurality of data lines171, a plurality of source electrodes 173 a and 173 b, a plurality ofdrain electrodes 175 a and 175 b, and a plurality of data pads (notshown).

Then, portions of the ohmic contact layer 160 a and 160 b, which are notcovered by the source electrodes 173 a and 173 b and the drainelectrodes 175 a and 175 b, are removed such that an ohmic contact layer163 a, 163 b, 165 a and 165 b including a plurality of separatedportions is formed and portions of the semiconductor layer 153 betweenthe source electrodes 173 a and 173 b and the drain electrodes 175 a and175 b are exposed.

As shown in FIG. 3D, a passivation layer 180 is formed by coating anorganic insulating material having low dielectric constant and goodplanarization characteristic or by CVD of low dielectric insulatingmaterial such as SiOF or SiOC having a dielectric constant equal to orless than 4.0. The passivation layer 180 together with the gateinsulating layer 140 is patterned by a photo-etching step using a maskto form a plurality of contact holes 181, 182 and 183.

Finally, as shown in FIG. 2A, an ITO layer or an IZO layer withthickness of 1500-500 Å is deposited and photo-etched using a mask toform a plurality of pixel electrodes 190, a plurality of connectingbridges 92, a plurality of subsidiary gate pads (not shown) and aplurality of subsidiary data pads (not shown).

This technique is applied to a manufacturing method using five masks asdescribed above. However, the technique may be well adapted for a methodof a TFT array panel for an LCD using four masks. It is described indetail with reference to the drawings.

FIG. 4 is a layout view of a TFT array panel for an LCD according to asecond embodiment of the present invention, and FIG. 5 is a sectionalview of the TFT array panel shown FIG. 4 taken along the lines V-V′ andV′-V″.

A TFT array panel for an LCD according to a second embodiment of thepresent invention is manufactured by using four masks and has a featurecompared with a TFT array panel manufactured by using five masks, whichwill be described now.

An ohmic contact layer 161, 163 a, 163 b, 165 a, 165 b and 168 formedunder a plurality of DCEs 176 and a data wire including a plurality ofdata lines 171, a plurality of source electrodes 173 a and 173 b, aplurality of the drain electrodes 175 a and 175 b, and a plurality ofdata pads 179 has substantially the same shape as the data wire 171, 173a, 173 b, 175 a, 175 b and 179 and the DCEs 176. An amorphous siliconlayer 151 a, 151 b, 153 and 158 has substantially the same shape as thedata wire and the DCEs 176 except that channel portions between thesource electrodes 173 a and 173 b and the drain electrodes 175 a and 175b are connected. Remaining structure is substantially the same as a TFTarray panel manufactured by a five-mask process.

FIG. 4 illustrates a gate pad 125, a storage pad 135 and a data pad 179as well as a subsidiary gate pad 95, a subsidiary storage pad 99 and asubsidiary data pad 97.

A method of manufacturing a TFT array panel will be now described.

FIGS. 6A to 11B are layout views and sectional views of a TFT arraypanel for an LCD sequentially illustrating a manufacturing methodthereof.

First, as shown in FIGS. 6A and 6B, Al, Ag, their alloys or the like isdeposited and photo-etched to form a gate wire including a plurality ofgate lines 121, a plurality of gate pads 125 and a plurality of gateelectrodes 123, and a storage electrode wire 131 and 133 a-133 d. (FirstMask)

As shown in FIG. 7, a silicon nitride gate insulating layer 140 with1,500-5,000 Å thickness, an amorphous silicon layer 150 with 500-2,000 Åthickness, and a contact layer 160 with 300-600 Å thickness aresequentially deposited by CVD. A conductive layer 170 preferably made ofAl, Ag or their alloys is deposited by preferably sputtering, and aphotoresist film PR with thickness of 1-2 microns is coated thereon.

Thereafter, the photoresist film PR is exposed to light through a maskand is developed to form a photoresist pattern including a plurality offirst portions PR1 and a plurality of second portions PR2 as shown inFIGS. 8A and 8B. Each second portion PR2 of the photoresist pattern PR1and PR2 located on a channel area C of a TFT, which is placed between asource electrode 173 a or 173 b and a drain electrode 175 a or 175 b, isthicker than each first portion PR1 of the photoresist pattern locatedon a data area A where a data wire will be formed. All portions of thephotoresist film PR on the remaining areas B are removed. Here, theratio of the thickness of the photoresist pattern PR1 and PR2 on thechannel area C and on the data area A is adjusted depending on processconditions of subsequent etching steps described later, and it ispreferable that the thickness of the second portion PR2 is equal to orless than a half of that of the first portion PR1, for example, equal toor less than 4,000 Å. (Second Mask)

The position-dependent thickness of the photoresist pattern is obtainedby several techniques. A slit pattern, a lattice pattern or atranslucent film is provided on the mask in order to adjust the lighttransmittance in the area C.

When using a slit pattern, it is preferable that width of the slits anda gap between the slits is smaller than the resolution of an exposerused for the photolithography. In case of using a translucent film, thinfilms with different transmittances or different thickness may be usedto adjust the transmittance on the masks.

When a photoresist film is exposed to light through such a mask,polymers of a portion directly exposed to the light are almostcompletely decomposed, and those of a portion exposed to the lightthrough a slit pattern or a translucent film are not completelydecomposed because the amount of a light irradiation is small. Thepolymers of a portion of the photoresist film blocked by alight-blocking film provided on the mask are hardly decomposed. Afterthe photoresist film is developed, the portions containing the polymers,which are not decomposed, is left. At this time, the thickness of theportion with less light exposure is thinner than that of the portionwithout light exposure. Since too long exposure time decomposes all themolecules, it is necessary to adjust the exposure time.

The small thickness of the second portion PR2 of the photoresist patternmay be obtained using reflow. That is, the photoresist film is made of areflowable material and exposed to light through a normal mask havingopaque and transparent portions. The photoresist film is then developedand subject to reflow such that portions of the photoresist film flowsdown onto areas without photoresist, thereby forming thin portions.

Next, the photoresist pattern PR1 and PR2 and the underlying layersincluding the conductive layer 170, the contact layer 160 and thesemiconductor layer 150 are etched such that the data wire and theunderlying layers are left on the data areas A, only the semiconductorlayer is left on the channel areas C, and all the three layers 170, 160and 150 are removed to expose the gate insulating layer 140 on theremaining areas B.

First, as shown in FIG. 9, the exposed portions of the conductive layer170 on the other areas B are removed to expose the underlying portionsof the contact layer 160. Both dry etch and wet etch are selectivelyused in this step and preferably performed under the condition that theconductive layer 170 is easily etched and the photoresist pattern PR1and PR2 are hardly etched. However, since it is hard to identify theabove-described condition for dry etch, and the dry etch may beperformed under the condition that the photoresist pattern PR1 and PR2and the conductive layer 170 are etched simultaneously. In this case,the second portions PR2 of the photoresist pattern on the channel areasC for dry etch are preferably made to be thicker than those for the wetetch to prevent the removal of the second portions PR2 of thephotoresist pattern on the channel areas C and thus the exposure of theunderlying portions of the conductive layer 170.

As a result, as shown in FIG. 9, only the portions 171, 170 a and 170 bof the conductive layer 170 on the channel areas C and the data areas Aare left and the portions of the conductive layer 170 on the remainingareas B are removed to expose the underlying portions of the contactlayer 160. Here, the data-wire conductors 171, 170 a and 170 b havesubstantially the same planar shapes as the data wire 171, 173 a, 173 b,175 a, 175 b and 179 except that the source electrodes 173 a and 173 band the drain electrodes 175 a and 175 b are not disconnected from butconnected to each other. When using dry etch, the thickness of thephotoresist pattern PR1 and PR2 is reduced to an extent.

Next, as shown in FIG. 9, the exposed portions of the contact layer 160and the underlying portions of the amorphous silicon layer 150 on theareas B as well as the second portions PR2 of the photoresist pattern onthe channel areas C are removed by dry etch. The etching is performedunder the condition that the photoresist pattern PR1 and PR2, thecontact layer 160 and the semiconductor layer 150 are easily etched andthe gate insulating layer 140 is hardly etched. (It is noted thatetching selectivity between the intermediate layer and the semiconductorlayer is nearly zero.) In particular, it is preferable that the etchingratios for the photoresist pattern PR1 and PR2 and the semiconductorlayer 150 are nearly the same. For instance, the etched thicknesses ofthe photoresist pattern PR1 and PR2 and the semiconductor layer 150 canbe nearly the same by using a gas mixture of SF₆ and HCl, or a gasmixture of SF₆ and O₂. When the etching ratios for the photoresistpattern PR1 and PR2 and for the semiconductor pattern 150 are the same,the initial thickness of the second portions PR2 of the photoresistpattern on the channel areas C is equal to or less than the sum of thethickness of the semiconductor layer 150 and the thickness of thecontact layer 160.

Consequently, as shown in FIG. 10, the second portions PR2 of thephotoresist pattern on the channel areas C are removed to expose theunderlying portions of source/drain (“S/D”) conductors 170 a and 170 b,and the portions of the contact layer 160 and the semiconductor layer150 on the remaining areas B are removed to expose the underlyingportions of the gate insulating layer 140. In the meantime, the firstportions PR1 of the photoresist pattern on the data areas A are alsoetched to become thinner. Moreover, the semiconductor pattern 151 a, 151b, 153 and 158 is completed in this step. A plurality of ohmic contacts161, 160 a, 160 b and 168 are formed on the semiconductor pattern 151 a,151 b, 153 and 158.

Then, photoresist remnants left on the surface of the S/D conductors 170a and 170 b on the channel areas C are removed by ashing.

Next, as shown in FIGS. 11A and 11B, portions of the S/D conductors 170a and 170 b and the underlying portions of the S/D ohmic contacts 160 aand 160 b on the channel areas C are etched to be removed. Here, theetching of both the S/D conductors 170 a and 170 b and the S/D ohmiccontacts 160 a and 160 b may be done using only dry etching.Alternatively, the S/D conductors 170 a and 170 b are etched by wetetching and the S/D ohmic contacts 160 a and 160 b are etched by dryetching. In the former case, it is preferable to perform the etchingunder the condition that etching selectivity between the S/D conductors170 a and 170 b and the S/D ohmic contacts 160 a and 160 b is high. Itis because the low etching selectivity makes the determination of theetching finish point difficult, thereby causing the adjustment of thethickness of the portions of the semiconductor pattern 151 a and 151 bleft on the channel areas C to be difficult. In the latter casealternately applying wet etching and dry etching, a stepwise lateralsidewall is formed since the wet etch etches the lateral sides of theS/D conductors 170 a and 170 b, while the dry etch hardly etches thelateral sides of the S/D ohmic contacts 160 a and 160 b. Examples ofetching gases used for etching the S/D ohmic contacts 160 a and 160 bare a gas mixture of CF₄ and HCl and a gas mixture of CF₄ and O₂. Use ofthe gas mixture of CF₄ and O₂ enables to obtain uniform thickness ofetched portions of the semiconductor pattern 151 a and 151 b. In thisregard, the exposed portions of the semiconductor pattern 151 a and 151b are etched to have a reduced thickness, and the first portions PR1 ofthe photoresist pattern on the data-wire areas A are also etched to havea reduced thickness. This etching is performed under the condition thatthe gate insulating layer 140 is not etched, and it is preferable thatthe photoresist pattern is thick enough to prevent the first portionsPR1 of the photoresist pattern on the data-wire areas A from beingremoved to expose the underlying portions of the data wire 171, 173 a,173 b, 175 a, 175 b and 179.

Accordingly, the source electrodes 173 a and 173 b and the drainelectrodes 175 a and 175 b are separated from each other, and,simultaneously, the data wire 171, 173 a, 173 b, 175 a, 175 b and 179and the ohmic contact pattern 161, 163 a, 163 b, 165 a and 165 bthereunder are completed.

Finally, the first portions PR1 of the photoresist pattern left on thedata areas A are removed. Alternatively, the first portions PR1 of thephotoresist pattern on the data areas A are removed after the portionsof the S/D conductors 170 a and 170 b on the channel areas C are removedand before the underlying portions of the S/D ohmic contacts 160 a and160 b are removed.

As described above, wet etching and dry etching may be performed oneafter the other, but only dry etching may be used. The latter isrelatively simple but it is not easy to find a proper etching conditioncompared with the former. On the contrary, it is easy to find a properetching condition for the former case but the former is relativelycomplicated compared with the latter.

Thereafter, as shown in FIGS. 4 and 5, a passivation layer 180 is formedby growing a-Si:C:O or a-Si:O:F by CVD, by depositing silicon nitride,or by coating an organic insulating material such as acryl-basedmaterial. When forming an a-Si:C:O layer, SiH(CH₃)₃, SiO₂(CH₃)₄,(SiH)₄O₄(CH₃)₄, Si(C₂H₅O) or the like used as basic source, oxidant suchas N₂O or O₂, and Ar or He are mixed in gaseous states to flow for thedeposition. For an s-Si:O:F layer, the deposition is performed withflowing a gas mixture including SiH₄, SiF₄ or the like and an additionalgas of O₂. CF₄ may be added as a secondary source of fluorine.

As shown in FIGS. 4 and 5, the passivation layer 180 together with thegate insulating layer 140 is photo-etched to form a plurality of contactholes 181, 182, 183, 184, 185 and 186 exposing the first drainelectrodes 175 a, the second source electrodes 173 b, the storageelectrode lines 131, the gate pads 125, the storage pads 135 and thedata pads 179. It is preferable that the area of the contact holes 184,185 and 186 exposing the pads 125, 179 and 135 is equal to or largerthan 0.5 nm×15 μm and not larger than 2 mm×60 μm. (Third Mask)

Finally, an ITO layer or an IZO layer with a thickness of 1500-500 Å isdeposited and photo-etched to form a plurality of pixel electrodes 190connected to the drain electrodes 175, a plurality of subsidiary gatepads 95 connected to the gate pads 125, a plurality of subsidiary datapads 97 connected to the data pads 179, and a plurality of bridges 92connecting the second source electrodes 173 b and the storage electrodelines 131. (Fourth Mask)

Since Cr etchant can be used as an etchant for an IZO layer, the exposedportions of the metal for the data wire and the gate wire through thecontact holes are not corroded in the photo-etching step for forming thepixel electrodes 190, the subsidiary gate pads 95, the subsidiary datapads 97 and the bridges 92 from the IZO layer. An example of the Cretchant is (HNO₃/(NH₄)₂Ce(NO₃)₆/H₂O). The IZO layer is deposited attemperature preferably in a range from a room temperature to 200° C. forminimizing the contact resistance at the contacts. A preferred exampleof a target for the IZO layer includes In₂O₃ and ZnO. The content of ZnOis preferably in a range between 15 atm % and 20 atm %.

Meanwhile, nitrogen gas is preferably used for the pre-heating processbefore the deposition of the ITO layer or the IZO layer. This is toprevent the formation of metal oxides on portions of the metallic layersexposed through the contact holes 181, 182, 183, 184, 185 and 186.

FIG. 12 is a schematic diagram of the TFT array panels for an LCD shownin FIGS. 2A and 4 according to an embodiment of the present invention.

A TFT T1 connected to a data line 171 switches signals transmitted to apixel electrode 190 while a TFT T2 connected to a storage electrode lineswitches signals entering a DCE 176. The pixel electrode 190 and the DCE176 are capacitively coupled. For the same gray, there is no variationof the potential difference between the DCE 176 and the pixel electrode190. Therefore, stability of image quality is ensured irrespective ofinversion types such as line inversion, dot inversion or the like.Furthermore, there is an advantage that there is no increase of the loadof the data lines.

FIG. 13 is a picture image on an LCD according to an embodiment of thepresent invention.

As shown in FIG. 13, an LCD according to the present invention showsexcellent image quality with reduced unstable textures.

Although preferred embodiments of the present invention have beendescribed in detail hereinabove, it should be clearly understood thatmany variations and/or modifications of the basic inventive conceptsherein taught which may appear to those skilled in the present art willstill fall within the spirit and scope of the present invention, asdefined in the appended claims.

As described above, there is no variation of the potential differencebetween the DCE 176 and the pixel electrode 190 for the same gray, bymaking a TFT connected to a data line 171 switch signals transmitted toa pixel electrode 190 while a TFT connected to a storage electrode lineswitch signals entering a DCE 176 and by capacitively coupling the pixelelectrode 190 and the DCE 176. Therefore, stability of image quality isensured irrespective of inversion types such as line inversion, dotinversion or the like. Furthermore, there is an advantage that there isno increase of the load of the data lines.

1. A thin film transistor array panel comprising: an insulatingsubstrate; a plurality of first signal lines formed on the insulatingsubstrate; a plurality of second signal lines formed on the insulatingsubstrate, insulated from the first signal lines, and intersecting thefirst signal lines; a plurality of third signal lines formed on theinsulating substrate, insulated from the second signal lines, andintersecting the second signal lines; a plurality of pixel electrodesprovided on respective pixel areas defined by the intersections of thefirst and the second signal lines, each pixel electrode having a cutout;a plurality of direction control electrodes provided on the respectivepixel areas defined by the intersections of the first and the secondsignal lines; a plurality of first thin film transistors, each firstthin film transistor connected to one of the first signal lines, one ofthe second signal lines, and one of the pixel electrodes; and aplurality of second thin film transistors, each second thin filmtransistor connected to one of the first signal lines, one of the thirdsignal lines, and one of the direction control electrodes.
 2. The thinfilm transistor array panel of claim 1, wherein one of the first thinfilm transistors and one of the second thin film transistor located onone of the pixel areas are connected to a relevant one of the firstsignal lines and a previous one of the first signal lines.
 3. Theapparatus of claim 1, wherein the direction control electrode overlapsthe cutouts of the pixel electrode at least in part.
 4. A thin filmtransistor array panel comprising: an insulating substrate; a gate wireformed on the insulating substrate and including first and second gateelectrodes and a plurality of gate lines; a storage electrode wireformed on the insulating substrate and including a plurality of storageelectrode lines and a plurality of storage electrodes; a gate insulatinglayer formed on the gate wire and the storage electrode wire; asemiconductor layer formed on the gate insulating layer; a data wireformed on the semiconductor layer and including a plurality of datalines intersecting the gate lines, a plurality of first sourceelectrodes connected to the data lines, a plurality of first drainelectrodes opposite the first source electrodes with respect to thefirst gate electrodes, a plurality of second source electrodeselectrically connected to the storage electrode wire, and a plurality ofsecond drain electrodes opposite the second source electrodes withrespect to the second gate electrodes; a direction control electrodeconnected to the second drain electrode; a passivation layer formed onthe data wire and the direction control electrode and having a pluralityof contact holes; and a pixel electrode formed on the passivation layer,having a plurality of cutouts, and electrically connected to the firstdrain electrodes through the contact holes.
 5. The thin film transistorarray panel of claim 4, where in the direction control electrodeoverlaps the cutouts of the pixel electrode at least in part.
 6. Thethin film transistor array panel of claim 5, wherein the cutouts of thepixel electrode comprise a plurality of X-shaped cutouts and a pluralityof rectilinear cutouts and the direction control electrode overlaps theX-shaped cutouts.
 7. The thin film transistor array panel of claim 5,wherein the semiconductor layer comprises a plurality of data portionsdisposed under the data lines, a plurality of first channel portionsdisposed under the first source electrodes and the first drainelectrodes, and a plurality of second channel portions disposed underthe second source electrodes and the second drain electrodes.
 8. Thethin film transistor array panel of claim 4, further comprising aplurality of connecting members formed on the passivation layer andconnecting the second source electrodes and the storage electrode wirethrough contact holes provided at the passivation layer and the gateinsulating layer.
 9. The thin film transistor array panel of claim 5,wherein the direction control electrode includes substantially the samelayer and material as the data wire.
 10. A liquid crystal displaycomprising: a first insulating substrate; a plurality of first signallines formed on the first insulating substrate; a plurality of secondsignal lines formed on the first insulating substrate, insulated fromthe first signal lines, and intersecting the first signal lines; aplurality of third signal lines formed on the first insulatingsubstrate, insulated from the second signal lines, and intersecting thesecond signal lines; a plurality of pixel electrodes provided on therespective pixel areas defined by the intersections of the first and thesecond signal lines, each pixel electrode having a cutout; a pluralityof direction control electrodes provided on the respective pixel areasdefined by the intersections of the first and the second signal lines; aplurality of switching elements, each first switching element connectedto one of the first signal lines, one of the second signal lines, andone of the pixel electrodes; a plurality of second thin filmtransistors, each second switching element connected to one of the firstsignal lines, one of the third signal lines, and one of the directioncontrol electrodes; a second insulating substrate opposite the firstinsulting substrate; a common electrode formed on the second insulatingsubstrate; and a liquid crystal layer interposed between the firstinsulating substrate and the second insulating substrate.
 11. The liquidcrystal display of claim 10, wherein the third signal lines are suppliedwith a voltage to be applied to the common electrode.
 12. The liquidcrystal display of claim 11, wherein the liquid crystal layer hasnegative dielectric anisotropy and major axes of liquid crystalmolecules in the liquid crystal layer are aligned vertical to the firstand the second substrates.
 13. The liquid crystal display of claim 11,wherein the liquid crystal layer has positive dielectric anisotropy andmajor axes of liquid crystal molecules in the liquid crystal layer arealigned parallel to the first and the second substrates.
 14. Theapparatus of claim 10, wherein the direction control electrode overlapsthe cutouts of the pixel electrode at least in part.
 15. A thin filmtransistor array panel comprising: an insulating substrate; a gate wireformed on the insulating substrate; a storage electrode wire formed onthe insulating substrate; a gate insulating layer formed on the gatewire and the storage electrode wire; a data wire formed on the gateinsulating layer including three layers an amorphous silicon layer, adoped amorphous silicon layer, and a metal layer; a direction controlelectrode formed on the gate insulating layer, including three layers anamorphous silicon layer, a doped amorphous silicon layer, and a metallayer, and electrically connected to the second drain electrode; apassivation layer formed on the data wire and the direction controlelectrode and having a plurality of contact holes; and a pixel electrodeformed on the passivation layer, having a plurality of cutouts, andelectrically connected to the data wire through the contact holes. 16.The thin film transistor array panel of claim 15, wherein the gate wirecomprises first and second gate electrodes, the data wire comprisesfirst and second source electrodes and first and second drainelectrodes, the direction control electrode is connected to the seconddrain electrode, the pixel electrode is connected to the first drainelectrode, and the second source electrode is connected to the storageelectrode wire.
 17. The thin film transistor array panel of claim 16,further comprising a connecting member formed on the passivation layerand connecting the second source electrode and the storage electrodewire through a contact hole provided at the passivation layer and thegate insulating layer.
 18. A method of manufacturing a thin filmtransistor array panel, comprising: forming a gate wire and a storageelectrode wire; depositing a gate insulating layer, an amorphous siliconlayer, a contact layer, and a metal conductive layer; patterning theamorphous silicon layer, the contact layer, and the metal conductivelayer to form a data wire, a direction control electrode, and a channelportion of a thin film transistor; forming a passivation layer on thechannel portion; forming a pixel electrode on the passivation layer;forming a plurality of connecting members on the passivation layer;forming a plurality of source electrodes electrically connected to thestorage electrode wire; and connecting the source electrodes and thestorage electrode wire through contact holes provided at the passivationlayer and the gate insulating layer.
 19. The method of claim 18, whereinthe pixel electrode includes a plurality of cutouts, the directioncontrol electrode overlaps the cutouts of the pixel electrode at leastin part.